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With billions of chips in the market, RISC-V has seen widespread commercial adoption across industries and implementations, from embedded automotive to hyperscale AI, from 5G to HPC and beyond.

Zurich – Dec. 6, 2021RISC-V International, a global open hardware standards organization, is bringing the open hardware community together to network, learn, celebrate, and fuel the open era of microprocessor design at the RISC-V Summit, which is being held virtually and in-person in San Francisco from Dec. 6-8, 2021.

RISC-V commitment and investment continues to skyrocket with RISC-V membership growing 130% in 2021 to 2,478 members including 18 Premier level members. Engagement in RISC-V work groups and committees has grown 67% in the last year to nearly 12,000 individuals. The contributions and commitment of the RISC-V community are clearly reflected in the historic technical progress as well as the industry innovation and traction of commercial solutions. Furthermore, RISC-V anticipates that in 2021 alone there will be two billion RISC-V cores on the market.

This year, the global RISC-V community made significant technical strides through streamlined governance, stakeholder engagement, and global collaboration. RISC-V technical progress has benefited the community with exemplary member programs such as RISC-V Development Partners, RISC-V Labs, and RISC-V Developer Boards. RISC-V also deepened its commitment to support industry talent through several new online education courses, expanded relationships with academic institutions, the launch of RISC-V Mentorships, and the creation of the Open Hardware Diversity Alliance.

“RISC-V is proving the power of open collaboration in driving the silicon industry forward with incredible technical advancements, deep global collaboration, and profound innovations across the full spectrum of computing. In 2021, RISC-V has seen unprecedented membership growth in parallel with the rising adoption of RISC-V across markets and geographies,” said Calista Redmond, CEO of RISC-V. “I am both proud and grateful for the strategic investment and collaboration of RISC-V members in their technical contributions as we together build RISC-V as the ISA for the open era of computing.”

In 2021, RISC-V continued to focus on driving progression and ratification of standards and technical deliverables. Last week, RISC-V announced its ratification of 15 new specifications. These specifications, which include the Vector, Scalar Cryptography, and Hypervisor specifications, will help unlock new opportunities for developers creating RISC-V applications for AI, ML, the IoT, connected and autonomous cars, data centers, and beyond. In February, RISC-V unveiled its Fast Track Architecture Extension Process (Fast Track) that streamlines the ratification of small architecture extensions. Fast Track defines the process for developing and standardizing architecture extensions that meet specific criteria, while providing reasonable quality control under the oversight and approval of the relevant RISC-V standing committee. In correlation, the new Fast Track process ratified the first extension, ZiHintPause, which allows engineers to reduce the energy consumption of their designs, improves the performance of spin-wait loops, and enables multithreaded cores to temporarily relinquish extension resources by adding a single PAUSE instruction (encoded as a HINT instruction) to the ISA.

Additionally, RISC-V expanded its industry alliances to engage a broad community of stakeholders across both technical and non-technical topics that help the open source community and industries using RISC-V technology. To increase the security features that encompass the ISA, seL4 Foundation and RISC-V verified seL4 microkernel on the RV64 architecture which guarantees that the microkernel will operate to specification even when built with an untrusted C compiler, GCC. Together RISC-V and seL4’s collaboration enables stronger security, combining security-oriented architecture and operating system design. In addition, RISC-V and CHIPS Alliance formed a new OmniXtend working group that focuses on creating an open, cache coherent, unified memory standard for multicore compute architectures to make it easier for designers to take advantage of OmniXtend for data-centric applications.

Founded in collaboration among RISC-V, CHIPS Alliance, OpenPOWER Foundation, and Western Digital, the Open Hardware Diversity Alliance was launched to provide support programs, learning opportunities, and mentorships for women and underrepresented individuals in the open hardware community. By providing a supportive community, the program will help to drive professional growth, empower the development of technical careers, encourage the recognition of all ideas in technical innovations, and support career growth.

Together with The Linux Foundation, RISC-V launched three free online courses to empower individuals to better understand how to implement and utilize RISC-V. The courses have been among the most popular courses in LF history with 8,842 enrollments in the first nine months. The first course, Introduction to RISC-V (LFD110x), provides the foundational knowledge needed to effectively engage in the RISC-V community, contribute to the ISA specifications, and develop a wide range of RISC-V software and hardware projects. The second course, Building a RISC-V CPU Core (LFD111x), focuses on digital logic design and basic central processing unit (CPU) microarchitecture and allows participants to familiarize themselves with a variety of emerging technologies supporting an open source hardware ecosystem, including RISC-V, transaction-level verilog, and the online Makerchip IDE. The third course, RISC-V Toolchain and Compiler Optimization Techniques, is designed for RISC-V application developers looking to improve performance or reduce the code size of their applications, toolchain developers, compiler engineers/performance engineers, and computer science students aspiring to major in systems software.

The RISC-V community grew their contributions to RISC-V projects, collaborating together, and commercializing RISC-V hardware and software solutions.

Notable achievements of RISC-V adoption in 2021 include:

  • Antmicro added support for the RVV 1.0 vector instructions to its open source Renode simulation framework, allowing users to enhance their machine learning development experience in a purely virtual environment. RISC-V Vector ISA support will be one of the highlights of the upcoming Renode 1.13 release.
  • Altair Engineering India Pvt Ltd. announced its collaboration with the Indian Institute of Technology Madras (IITM) to add the Shakti processor, India’s first indigenous RISC-V processor, to the support portfolio of Altair Embed.
  • HPMicro and Andes Technology joint announced the HPM6000 series of Microcontrollers with AndesCore™ Dual D45 Cores, with a clock speed up to 800 MHz, setting a new performance record by over 9000 CoreMark and 4500 DMIPS.
  • IAR Systems announced the availability of RISC-V development tools with certification for IEC 61508 and ISO 26262, which specifies life cycle requirements for the development of medical software and devices, European railway standards, household appliances, and more.
  • IAR Systems released the complete development toolchain IAR Embedded Workbench® for RISC-V and added support for the latest Andes RISC-V extension and devices, enabling maximized performance in RISC-V-based applications.
  • CAST, Inc. announced the availability of EMSA5-FS, a fault-tolerant embedded RISC-V processor IP core designed to meet the most stringent functional safety requirements of automotive, airborne, and other safety-critical applications.
  • Imagination University Programme created the RVfpga: Understanding Computer Architecture teaching package that provides a set of instructions, tools, and labs about microarchitecture and memory hierarchy.
  • SemiDynamics’ Avispado 220 RV64GC core with the open vector interface was tapped into the European Processor Initiative “EPAC” acceleration chip.
  • Imperas Software Ltd. launched a multi-year distribution and support agreement with Valtrix Systems to address the rapidly expanding worldwide market for RISC-V processor verification.
  • Microchip Technology added a second development tool offering for designers using its low-power PolarFire® RISC-V® SoC FPGA for embedded vision applications at the edge.
  • ZAYA announced secure containers for RISC-V microcontrollers.
  • Axiomise unwrapped its expanded formal verification training program that now offers courses for beginners through experts to further the adoption of formal hardware verification and validation.
  • Ventana Micro Systems Inc. unveiled its compute chiplets to maximize performance by targeting cutting edge process geometries and allows customers to implement their unique SoC chiplet silicon in the most optimal process node for the target application.
  • Renesas Electronics Corporation and SiFive, Inc. announced a strategic partnership to jointly develop next-generation, high-end RISC-V solutions for automotive applications.
  • Esperanto Technologies announced its RISC-V-based inference chip, a parallel processing solution that can accelerate many parallelizable workloads.
  • Kneron Inc. announced mass production of its next-generation Edge AI SoC KL530, powered by Andes’ D25F processor with RISC-V Packed-SIMD DSP extension, whose reconfigurable architecture supports INT4 precision and a wide variety of AI models including Transformer.
  • A team at Technical University of Munich (TUM) designed and commissioned the production of a computer chip that implements post-quantum cryptography to provide protection against future hacker attacks using quantum computers.
  • Alibaba announced opening the source code of the XuanTie IP core series. The XuanTie series are Alibaba’s custom-built processors based on RISC-V instruction set architecture (ISA). The company has also been working on porting Android 10 to the RISC-V ISA over the past year as well.
  • org® and Seeed introduced the first affordable RISC-V board designed to run Linux.
  • StarFive Technology Co., Ltd. announced a “VisionFive” single-board computer for mid-to-high-end RISC-V applications development.
  • Imperas Software Ltd., updated its open-source reference models for RISC-V to now support the latest ratified extensions: Bit Manipulation, Cryptographic (scalar) and Vector, plus the Privilege Specification enhancements.
  • Intel will create a RISC-V development platform with SiFive P550 cores on 7nm in 2022.

To learn more about the free and open RISC-V ISA, please visit: https://riscv.org. To become a member of RISC-V International, please visit: https://riscv.org/membership/.

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About RISC-V International

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. RISC-V International comprises more than 2,400 members building the first open, collaborative community of software and hardware innovators powering an open era of processor innovation. The RISC-V ISA delivers a new level of free, extensible software and modular hardware, paving the way for the next 50 years of open computing design freedom and innovation.

RISC-V International, a non-profit organization controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of RISC-V International have access to and participate in the development of the RISC-V ISA specifications and related ecosystem.

To learn more about RISC-V, please visit: www.riscv.org

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