The RISC-V Zfinx Task Group is thrilled to announce the Zfinx extension (pronounced “z-f-in-x”) has entered the public review period. The Zfinx extension brings the much needed instructions for floating point in integer registers to the RISC-V ISA.

The current public review period includes consideration of the the following Zfinx extensions:

  • Zfinx – Single-precision floating point in integer registers
  • Zdinx – Double-precision floating point in integer registers
  • Zhinx – Half-precision floating point in integer registers
  • Zhinxmin – Minimal 16-bit half-precision floating point in integer registers

The review period (August 3 to September 17, 2021) is open and the public is encouraged to take part in the discussions. To respond to the public review, please email comments to the public isa-dev mailing list or add issues to the Zfinx GitHub repo. The Zfinx Task Group welcomes all input and appreciates the time and effort the community contributes by reviewing the specification.

During the public review period, corrections, comments, and suggestions will be gathered for review by the Zfinx Task Group. Any minor corrections and/or uncontroversial changes will be incorporated into the specification. Any remaining issues or proposed changes will be addressed in the public review summary report. If there are no issues that require incompatible changes to the public review specification, the unprivileged ISA committee will recommend the updated specifications be approved and ratified by the RISC-V Technical Steering Committee and the RISC-V Board of Directors.

You can view the extensions described in the PDF spec or view the source available in the GitHub repo.

RISC-V International would like to extend a special thank you to all the contributors for all their hard work, and especially to Chair of the Zfinx Task Group, Tariq Kurd of Huawei for their contribution to the RISC-V ISA and ecosystem.

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