RISC-V is so much more than just an ISA for processors. Because of the openness of RISC-V, we are seeing an increase in innovation around processing architectures. One such example is OmniXtend. It is based on the open cache coherent memory bus, Tilelink, which is often used to connect multiple RISC-V CPU cores in SoCs. OmniXtend takes this open standard one step further and allows the cache bus to work over an Ethernet fabric! The result is a new architecture where multiple devices can share main memory equally and be distributed. 

By having distributed or disaggregated systems, it removes the barriers of scalability inherent in traditional computers. No longer must the memory be on-board, but we can now create network-attached versions which can be scaled. Without RISC-V’s openness, the open cache coherent fabric OmniXtend would not be possible. The underlying hardware bus works by leveraging TileLink 1.8 and wrapping it in Ethernet frames in a fault tolerant and low latency implementation. The current version of OmniXtend is 1.0.3 and it has been developed in the open organization CHIPS Alliance.

Today the RISC-V and CHIPS Alliance OmniXtend working group is focusing on updating the OmniXtend specification and protocol, building out architectural simulation models and a reference register-transfer level (RTL) implementation, as well as creating a verification workbench. These tools for an open, standard unified memory coherency bus leveraging OmniXtend will make it easier for designers to take advantage of OmniXtend for data-centric applications.

To find out more about the current development status of OmniXtend and see how you can implement an FPGA version, register now for the Oct. 12 technical talk which is part of the virtual CHIPS Alliance Fall Workshop. You can check out the full program here, and register for free here.

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