This past month, the RISC-V Summit 2022 schedule was announced. The Summit, which will be held on December 12-14, 2022, is the industry’s leading RISC-V conference. Along with keynotes, member meetings, and breakout sessions, RISC-V has dedicated an entire day to Summit tutorials. These technical tutorials are hands-on learning opportunities that highlight RISC-V implementations across various industries.
Curious to learn more? Check out the impressive lineup of tutorials below:
High Level Sail Overview – Bill McSpadden, RISC-V International
In this tutorial, Bill McSpadden , RISC-V International, will present an overview of Sail. Bill will address the current status of the Sail language and the RISC-V Golden Model. It also will provide an overview of the Sail Cookbook, and how to use the RISC-V Golden model to run Architectural Compatibility tests.
Running the Architectural Compatibility Tests on your Model: Theory and Practice – Neel Gala & Pawan Kumar, Incore Semiconductor; Marc Karasek, Inspire Semiconductor
In this tutorial, the Incore Semiconductor team will discuss what an implementer must do to run the ACTs on their model, and share practical experiences from an implementer.
Performance Tools – Knute Lingaard, SiFive & Arup Chakraborty, Ventana Microsystems
In this tutorial, the team from Ventana Microsystems and SiFive will provide an overview of the current state of the art and how the WG is addressing these would be useful.
Choosing Appropriate Verification Techniques for Desired RISC-V Processor Quality – Aimee Sutton & Lee Moore, Imperas Software
In this tutorial, the Imperas Software team will present a structured approach to RISC-V processor verification. This tutorial will highlight the importance of a verification plan and metric-driven verification for RISC-V processor designs that are destined for silicon production.
Toolchains – Christoph Müllner, VRULL
In this tutorial, VRULL will give an overview of the RISC-V toolchain ecosystem with a focus on three aspects: using toolchains (toolchain flavors and their components, standardization of RISC-V specific behavior); contributing/improving toolchains (reporting issues, building toolchains, testing toolchains); and the current extension enablement status.
Side-Channel Attacks and Transient Execution Vulnerabilities & RISC-V CFI – Allison Randal, Rivos & Giorgos Christou, Forth
Side-Channel – In this tutorial, the Forth team will dive deep into the essential knowledge that every hardware engineer should have about side-channel attacks and the transient execution vulnerabilities. It also will address approaches to limit the impact for CPU and SoC designers, system integrators, and end users.
CFI – In this part of the tutorial, the Forth team is going to review the discussions that took part during the Control Flow Integrity Special Interest Group meetings.Take a deep dive in how the attacks evolved in order to bypass deployed defenses and discuss notable detection and protection techniques presented in academia. The tutorial will end with a short overview of what Forth proposes for RISC-V architecture.
Spike Usage and Adding A New RISC-V Extension Support to Spike – Eop Chen, SiFive
In this tutorial, SiFive will run through the structure of Spike that would be most useful for people who are thinking of adding an ISA extension.
Virtualization – Sandro Pinto, Universidade do Minho (Portugal)
In this tutorial, Universidade do Minho will cover the four main pillars for RISC-V virtualization. Firstly, the tutorial will cover the basics of the hypervisor extension and demonstrate multiple open-source artifacts with upstream support for this extension: hypervisors, CPUs, and tools. Secondly, the tutorial will introduce the Advanced Interrupt Architecture (AIA) and discuss the existing support for virtualization. Thirdly, the tutorial will overview the Input-Output Memory Management Unit (IOMMU) draft specification and discuss the importance of avoiding fragmentation. Finally, the last part will focus on nested virtualization, in particular on the fundamental limitations of the existing support.
QEMU – Alistair Francis, WDC
In this tutorial, WDC will provide an introduction and overview of QEMU, how it can be used to run and test RISC-V software. He also will address how to develop new RISC-V extensions using QEMU.
For more information on the RISC-V Summit 2022, please visit our website.