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What to see at Embedded World 2023

RISC-V is leading the inevitable era of open computing at Embedded World 2023 in Nuremberg from March 14-16, as we bring the community together to show the power of open collaboration on innovation, product successes across the ecosystem, and the technical strength of RISC-V.

The RISC-V pavilion, 4A-620, will feature a range of member companies who will be showing demonstrations, delivering talks, and discussing the future of RISC-V-based computing from Android to Autonomous Vehicles.

Explore the member companies below, find out more about their technologies and discover the talks they will be giving in our Demo Theatre.

We look forward to seeing you at Embedded World 2023!


Demo Theatre:

Title: Expanding the RISC-V Horizon and Beyond

Speaker: Florian Wohlrab, Head of Sales EMEA & Japan, Andes Technology

Details: Tuesday March 14, 2023 13:00 – 13:15 CET & Wednesday March 15, 2023 12:00 – 12:15 CET, Hall 4A, Stand 4A-620,

Abstract: RISC-V ecosystem is growing in an unprecedented speed and Andes is a key driving force by offering rich processor IP solutions. In this talk, we will show a wide range of applications which have adopted RISC-V solutions and we will introduce new product lines to further expand the RISC-V horizon.

Empowering RISC-V with open source innovation from Ubuntu

We are proud to join RISC-V at Embedded World again in 2023! Our team will demo Ubuntu on RISC-V boards as well as demonstrate the potentials of open source innovation with our partners. 

Linux Made Easy on RISC-V with Ubuntu

Open standards and collaboration are strategic to hardware and software across industries and geographies. Open source and standards have reshaped our world in the last decade. RISC-V is the most prolific and open Instruction Set Architecture (ISA) in history, which has led the hardware community to embrace open standards and collaboration at this level. This open ISA enables a new era of processor innovation through open-standard collaboration with rapid industry-wide adoption.

While RISC-V enables stable reference architectures and hardware, running stable software on new boards can still be challenging. The cornerstone of the necessary software is the underlying Operating System (OS), which provides reliability and stability. This demand makes development on Linux even more attractive since Linux is the most popular OS for developers and hobbyists across kernels, drivers, and distributions.

At Canonical, we believe that open source is the best way to accelerate innovation. It motivates us to enable a wide range of open source communities under the Ubuntu umbrella. However, open source software comes with its own set of challenges. Canonical aims to position Ubuntu as not just the reference OS for innovators and developers but also as the vehicle to enable them to take their products to market faster by letting them focus on their core application without worrying about the stability of the underlying frameworks. 

Canonical has worked with silicon partners in the RISC-V ecosystem to bring Ubuntu to multiple RISC-V development boards. With the collaboration, Ubuntu is available on a variety of RISC-V development boards, including SiFive’s Unmatched and Unleashed, Allwinner’s Nezha D1, StarFive’s VisionFive, and Sipeed’s LicheeRV.

Demo Theatre:

Title: Ubuntu on RISC-V

Speaker: Heinrich Schuchardt, RISC-V lead engineer, Canonical

Details: Tuesday, March 14, 11:00 – 11:15, Hall 4A, Stand 4A-620

Abstract: Delivering a Linux distribution for an architecture in plain development is an exciting journey. The talk describes the challenges and opportunities seen while driving the RISC-V support in Ubuntu forward. We look at how Ubuntu delivers to the different market segments. A focus topic will be packages needed for high performance networking and storage.


Title: How to get RISC-V hardware fully “powered up” with excellent, secure and maintainable software

Speaker: Steve Barriault, Vice-President Field Engineering IoT

Details: Wednesday, March 15, 11:30 – 11:45, Hall 4A, Stand 4A-620

Abstract: It is a truism in the market that the best hardware does not always win races. A solid library of code that can be trusted and maintained is decisive for RISC-V to fulfil its promises. In this talk, Steve will discuss Canonical’s current efforts and future plans to help the community deliver innovative and secure RISC-V -based solutions.
This talk also will review the latest approaches for RISC-V verification including vector extension, PMP, crypto, privilege, and custom instructions with the ‘lock-step-compare’ method that supports asynchronous events and debug operations.

Demo Theatre:

Title: RISC-V Processor IP Product Line

Speaker: Alexander Kozlov, CTO, CloudBEAR

Details: Tuesday March 14, 2023 11:30 – 11:45 CET  & Wednesday March 15, 2023 11:00 – 11:15 CET, Hall 4A, Stand 4A-620

Abstract: CloudBEAR will be discussing their line of RISC-V Processor IP.

Demo Theatre:

Title: oneAPI with SYCL Gives Software Portability including Nvidia

Speaker: Charles Macfarlane, Chief Business Officer, Codeplay Software

Details: Tuesday March 14, 2023 13:30 – 13:45 CET & Wednesday March 15, 2023 13:00 – 13:15 CET, Hall 4A, Stand 4A-620

Abstract: oneAPI is an industry open standard and open source implementation which demonstrates portability across multiple platforms. Codeplay will demonstrate a CUDA application accelerated by Nvidia GPU and the same application migrated to SYCL running on the same Nvidia GPU.

Green Hills Software’s mature and proven safety-certified embedded software solutions for RISC-V enable the efficient development and cost-effective deployment of RISC-V-based designs in systems that require functional safety and security. In this session we will introduce Green Hills Software’s RISC-V offerings that feature certified real-time operating systems, C/C++ compilers and intuitive multicore debugging. Green Hills will also feature a RISC-V demonstration in its booth in Hall 4, Stand 325.

Demo Theatre:

Title: Enabling Production Program Software Development with Proven Safety-Certified Embedded Software Solutions for RISC-V

Speaker: Dan Mender, VP of Business Development, Green Hills Software

Details: Tuesday March 14, 2023 14:30 – 14:45 CET, Hall 4A, Stand 4A-620

Abstract: With RISC-V’s growing adoption and increased use in time critical, safety certified production programs, selecting the right software solutions is essential for the successful program deployment. Green Hills Software’s mature and proven safety-certified embedded software solutions for RISC-V enable the efficient development and cost-effective deployment of RISC-V-based designs in systems that require functional safety and security. In this session we will introduce Green Hills Software’s RISC-V offerings that feature certified real-time operating systems, C/C++ compilers and intuitive multicore debugging, drawing upon the company’s 40-years of successful customer program deployment experience.

Imperas is the leader in simulation solutions for RISC-V verification, and software development with virtual platforms and reference models for all the leading IP providers. The open standard of RISC-V offers developers new freedoms to explore new design flexibilities and enable innovations with optimized processors. The team from Imperas will be talking about design flows for custom instructions, and the latest advances with ‘lock-step-compare’ and coverage for RISC-V verification.

Demo Theatre:

Title: Introduction to RISC-V Processor Verification

Speaker: Larry Lapides, Vice President Sales, Imperas Software

Details: Tuesday March 14, 2023 10:30 – 10:45 CET, Hall 4A, Stand 4A-620

Abstract: The open standard RISC-V Instruction Set Architecture (ISA) offers developers new design freedoms for an optimized processor with all the benefits and advantages of full ecosystem support. RISC-V verification requires both functional tests and compliance to the ISA specification. Now all adopters that choose to explore the new design freedoms of
RISC-V will also need to consider the challenge of RISC-V verification.
This talk highlights the open standards such as RVVI (RISC-V Verification Interface) for test bench infrastructure that is supported with additional freely available resources with test suites, coverage libraries, and other Verification IP.
This talk also will review the latest approaches for RISC-V verification including vector extension, PMP, crypto, privilege, and custom instructions with the ‘lock-step-compare’ method that supports asynchronous events and debug operations.


Title: Getting Started with RISC-V Custom Instructions

Speaker: Jon Taylor, Director of Product Technology, Imperas

Details: Wednesday March 15, 2023 10:00 – 10:15 CET, Hall 4A, Stand 4A-620

Abstract: One of the attractive features of RISC-V is the ability to add, while maintaining ecosystem software support, new optimized instructions and extensions to a processor implementation. At first it appears as simple task to look at opportunities in the application code that could be accelerated with some dedicated new hardware. However, since hardware typically has a much longer life cycle than software, future updates and roadmap needs must be anticipated. Thus, the art of ISA design is using fine grain analysis to accelerate just the key steps while leaving sufficient flexibility to support new software updates and advances. Also, in multi-core arrays the use of custom extension can offer a lightweight communication channel between processors. This extends the scope beyond the processor itself into system design and analysis. This talk will illustrate the key profiling and analysis steps for custom extensions and optimization.

MachineWare will present SIM-V, an ultra-fast, SystemC TLM based, parallel-enabled, RISC-V instruction set simulator for early embedded software development and verification. SIM-V combines unprecedented simulation performance with full customizability for applications ranging from the tiniest embedded devices to warehouse-scale supercomputers. We enable software developers to test full software stacks – including firmware, operating system kernel and complex user-space applications, such as Java virtual machines or rich graphical environments – in real time. SIM-V addresses the need for high-performance RISC-V Loosely-Timed SystemC Virtual Platforms in application sectors like automotive electronics, AI, and telecom. It is based on MachineWare´s disruptive Just-In-Time compilation engine FTL (Fast Translator Library), enabling higher simulation performance, e.g. outperforming the current de facto industry standard QEMU by 2x. SIM-V supports Continuous Integration scenarios, where slow Virtual Platforms prohibit testing of every commit, and often only one daily run is possible, making it hard to pinpoint which exact change introduced the faulty behavior. At embedded world 2023, MachineWare will announce and demonstrate the first RISC-V based Virtual Platform with full support for Android 12. This will facilitate early software development for numerous upcoming embedded devices based on RISC-V chips.

Demo Theatre:

Title: Early RISC-V Software Verification with SIM-V

Speaker: Lukas Jünger, Managing Director, MachineWare GmbH

Details: Tuesday March 14, 2023 10:00 – 10:15 CET, Hall 4A, Stand 4A-620

Abstract: The RISC-V eco system is extremely dynamic. New processors and extensions are introduced at a high rate. At the same time, huge amounts of software are developed for, or ported to these new targets. Verifying the correct functionality of new software stacks is of paramount importance to release RISC-V products on-time and bug-free.This talk will introduce you to SIM-V, MachineWare’s fast RISC-V simulator for early software development and verification. With SIM-V large software stacks can be brought up and verified long before first prototypes are available.


Title: RISC-V Android Bring-Up using SIM-V

Speaker: Lukas Jünger, Managing Director, MachineWare GmbH

Details: Wednesday March 15, 2023 10:30 – 10:45 CET, Hall 4A, Stand 4A-620

Abstract: Today’s embedded software stacks are growing larger and larger every year. Booting an unmodified Android image requires executing more than 100 billion instructions and vendor-specific Android images even more. To verify these enormous amounts of software within reasonable time before physical prototypes are available, high-performance simulators are the go-to tool. This talk will give an introduction to verifying RISC-V Android using MachineWare’s high-performance SIM-V simulator.

Learn about the Industry’s Most Scalable RISC-V CPUs: Visit MIPS at Embedded World!

Across markets such as autonomous driving, Advanced Driver Assistance Systems (ADAS), datacenter, high performance computing, 5G communications and others, increasingly variable workloads are driving the need for heterogeneous computing. In this environment, what’s needed are highly scalable processing solutions that are configurable by threads, cores, and clusters, with shared memory between the cores, main memory and I/O devices.

MIPS has designed a new RISC-V eVocore P8700 multiprocessor with this in mind. The P8700 is the industry’s highest performance, most scalable RISC-V multiprocessor IP core, combining a deep pipeline with multi-issue Out-of-Order (OoO) execution and multi-threading to deliver outstanding computational throughput.

The P8700 can scale up to 64 clusters, 512 cores and 1,024 harts/threads. With P8700, designers can uniquely combine clusters of multi-threaded, multi-core CPUs (both eVocore processors and other accelerator) in unique configurations to achieve the right balance of performance and power consumption for their design. A Coherency Manager maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices.

The multi-threading capabilities in the P8700 provides additional advantages through a mechanism that enables switching to high-priority tasks with zero latency. Together with the hardware virtualization capability in the cores, this enables better utilization of system resources. 

Of course, while a highly scalable, efficient RISC-V CPU is a great starting point, it’s not enough. SoC designers today need solutions that will help them get to market quickly with proven, differentiated systems. We’re enabling this with secure, silicon-proven processors, as well as support for foundational technologies for specific applications such as automotive functional safety. In the P8700, this means proven robust safety capabilities for ISO 26262 ASIL-B(D) and ASIL-D systems. The P8700 is also the first CPU in silicon with support for automotive-grade Linux.

We will demonstrate the P8700 in the RISC-V booth (Hall 4A, Stand 620) at Embedded World. We will demonstrate software development tools that enable easy application development from project management through debug. We will also demonstrate benchmarks with single- and multi-threading capabilities to demonstrate the capabilities of the core.

Drop by our station to see the P8700 in action. Learn why the P8700 has been nominated for one of this year’s coveted Embedded World embedded awards, and why Mobileye, an industry leader in autonomous driving and advanced driver assistance systems (ADAS), has selected the P8700 for its next-generation EyeQ Ultra automotive vision processors.

You can also see MIPS technical experts present about the P8700 in the RISC-V theatre – see details below.

Demo Theatre:

  •   Tuesday, March 14 • 12:00 – 12:15

A Peek Inside a New RISC-V CPU for Autonomous Vehicles

Presented by Itai Yarom, Vice President of Sales & Marketing, MIPS

  •   Wednesday, March 15 • 13:30 – 13:45

RISC-V CPUs for the New Era of Heterogeneous Computing

Presented by Srinivas Kantheti, Senior Director of Software and Platforms, MIPS 

Visit MIPS at Embedded World!

RISC-V Booth: Hall 4A, Stand 620

Demo Theatre:

Title: Syntacore RISC-V IP

Speaker: Lisa Yang, Syntacore APAC Sales Represntative, Syntacore

Details: Tuesday March 14, 2023 14:00 – 14:15 CET  & Wednesday March 15, 2023 14:00 – 14:15 CET, Hall 4A, Stand 4A-620

Abstract: Syntacore will be discussing their line of RISC-V Processor IP.

Tiempo Secure announces TESIC RISC-V Secure Element IP and development kit

Building upon its longstanding expertise in semiconductor design, Tiempo Secure is proud to announce its TESIC RISC-V Secure Element IP, which brings an unprecedented level of security to the embedded systems environment, it is certification-ready for Common Criteria EAL 5+ level and makes SoC development easy thanks to its integration with the complete RISC-V ecosystem. Tiempo Secure also introduces its Development Kit allowing all RISC-V developers to build their own SoC benefitting from the security brought by its technologies.

Demo Theatre:

Title: A First Secure RISC-V Common Criteria Certified Root of Trust

Speaker: Serge Maginot, CEO, Tiempo Secure

Details: Tuesday March 14, 2023 15:00 – 15:15 CET, Hall 4A, Stand 4A-620

Abstract: Tiempo introduces a new generation of secure IP based on the RISC-V open instruction set. The hardware choices for embedded security are growing dynamically amid the push for higher levels of security for Internet of Things (IoT) devices, mobile devices and digital applications. One of the key drivers for better hardware security implementations is the increasing emphasis on security on these platforms to keep up with growing functionality and automation. With an “Off-the- Shelf approach”, the integration of its new TESIC Secure Enclave into systems on chips will be faster and easier for all SOC makers. Making “Secure Enclave” the new reference in terms of security integration for new and upcoming SOCs and platform. Certified to the highest standards in the industry, the solution is ready – to support and secure the most advanced applications (iSIM, Digital Identity, Crypto Currency…..)

ZAYA is a RISC-V Strategic Partner and develops security solutions for RISC-V Microcontrollers. RISC-V Security Monitor & Hypervisor is an all-in-one security solution that protects all device resources from external attacks and malfunctioning. ZAYA RISC-V Security, a.k.a ZAYA Secure OS, is a PSA Certified Operating System and meets IoT Security Certification and Regulation requirements. ZAYA RISC-V Security Monitor also offers Containerisation Technology, called ZAYA Microcontainers, for MMU-less RISC-V Microcontrollers to build secure, isolated and independent executions with controlled privileges(Microcontainer Access Policy). ZAYA Microcontainers are platform-agnostic environments, and the developer can use Microcontainers to run and protect native applications and even non-secure RTOSes like a Virtual machine. Microcontainers can also be used like a Microservice to run specific operations as design-time & run-time independent background services. Please visit the ZAYA booth and team, 4-123, to get more details about ZAYA RISC-V Solutions.

Demo Theatre:

Title: Certified Security and Containerisation for RISC-V Microcontrollers

Speaker: Murat Cakmak, Founder, CEO, ZAYA

Details: Wednesday March 15, 2023 14:30 – 14:45 CET Hall 4A, Stand 4A-620

Abstract: ZAYA RISC-V Security Monitor provides a rich TEE(Trusted Execution Environment) for RISC-V MCUs that do not even have built-in HW Security Peripherals. Certified ZAYA RISC-V Security Monitor handles all Security Certification Requirements, making End-User Applications security-free. ZAYA also brings Containerisation technology into MMU-less RISC-V Microcontrollers, called Microcontainers, to offer a secure, isolated, deployment-friendly and rich development environment for end-user application and Microservice development.

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