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[WEBINAR] Taking the Risk out of Developing Your Own RISC-V Processor with Fast, Architecture-Driven, PPA Optimization

Are you developing or thinking about developing your own RISC-V processor? You’re not alone. The use of the RISC-V ISA to develop processors for SoCs is a growing trend. RISC-V offers a lot of flexibility with the ability to customize or create ISA and microarchitectural extensions to differentiate your design no matter your application area: AI, machine learning, automotive, data center, mobile, or consumer. Proprietary cores with custom extensions are often highly complex and have traditionally required an equally elevated level of expertise to design them. Only those with deep knowledge and skills have successfully met the challenges associated with evaluating the impact of design decisions on power, performance, and area (PPA). But even experts can admit that this process can take an exceptionally long time and full optimization of these parameters may not be obtained.

Join us for a webinar replay and learn how to overcome these challenges and take the risk out of developing your own RISC-V processor.

Synopsys is dedicated to addressing the challenges facing RISC-V-based design with a portfolio of industry leading solutions that can bring RISC-V designs to life faster and easier. This Synopsys webinar will cover two tools:  Synopsys ASIP Designer and Synopsys RTL Architect. These tools can help chip designers create highly customized processors faster while meeting the desired PPA targets with confidence. We will also show these solutions in action with a real-world case study that will highlight their interoperability and the results that can be achieved.

Synopsys ASIP Designer is the leading tool-suite to design and program Application Specific Instruction-set Processors (ASIPs).  From a user-defined processor model, capturing the ASIP’s instruction-set and micro-architecture in the architecture description language nML, ASIP Designer automatically creates both a complete software development kit with an efficient C/C++ compiler, and a synthesizable RTL implementation of the ASIP.

The complexity of RISC-V chips and restrictive advanced node rules have made it more difficult for implementation tools to achieve power, performance, and area (PPA) targets. Synopsys RTL Architect is the industry’s first physical aware, RTL analysis, exploration, and optimization environment. The solution enables designers to “shift left” and predict the implementation impact of RTL significantly reducing RTL development time and creating better RTL.

This online seminar will present a new interoperability solution that facilitates a “Synthesis-in-the-Loop” design approach, both during earlier architectural design stages with processor model modifications and during RTL implementation.  Synopsys ASIP Designer’s RTL generation tool has been extended with an “ASIP RTL Explorer” utility that can systematically generate multiple RTL implementations of the ASIP with different design options.  Then, using Synopsys RTL Architect’s parallel exploration capabilities, designers can perform a comparative analysis of these RTL variants with respect to performance, power, and area (PPA).

We will illustrate the effectiveness of the new interoperability solution with a case study of a RISC-V ISA extended ASIP design for an AI-optimized MobileNet v3 inference, for which we want to find an energy-efficient implementation.  We will show how Synopsys ASIP Designer’s RTL Explorer generated 7 RTL variants for this ASIP and how Synopsys RTL Architect was used to compare and analyze the power consumption of these alternatives quickly and accurately.

The new interoperability solution reinforces Synopsys ASIP Designer’s Synthesis-in-the-Loop methodology and brings another productivity gain in the design of SoCs with programmable accelerators.

Join us for our Synopsys webinar to remove risk from your RISC-V processor development. Register today and watch the replay!

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