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Witnessing the Power of RISC-V at My First DAC

By: Sasha Ryu

This July, thousands of designers, researchers, tool developers, and vendors traveled to San Francisco to celebrate the 60-year anniversary of the Design Automation Conference (DAC), which took place from July 9-13, 2023. As a summer intern working with RISC-V International, I had the honor of being able to attend and see what all the hype for RISC-V is about.  

On Monday and Tuesday, crowds gathered in the RISC-V Zone Theater to watch presentations from RISC-V members across the industry. Below are some highlights:

  • Agile Analog explained how companies can use its RISC-V analog IP subsystem to simplify chip design and accelerate time to market.
  • CHIPS Alliance shared how the organization is fostering collaboration on open source hardware and software tools, along with its efforts to increase hardware security with the Caliptra project.
  • Codasip described how its data-driven design methodology makes it possible to harness the full potential of RISC-V.
  • Imperas discussed how companies can take advantage of custom RISC-V instructions to optimize its designs, and also went into detail about how to make RISC-V processor verification easy.
  • RISC-V International highlighted the momentum of RISC-V and gave an overview of the many RISC-V activities progressing around the globe.
  • Siemens shared how the RISC-V Trace Standard is helpful for debugging, and also talked about how to create domain-specific accelerators with Siemens EDA.

Each session at the RISC-V Zone Theater was packed, and it wasn’t just because we were giving attendees a raffle ticket to win one of our cool prizes. First, we gave out a 2,354-piece NASA Space Shuttle Discovery LEGO set, and then our second lucky winner got to take home the latest Meta Quest Pro VR Headset.

On Wednesday, I sat in on a RISC-V panel hosted by RISC-V International CEO Calista Redmond. The discussion—“Delivering on RISC V’s Promise to Give Designers Freedom to Innovate – What’s Needed?” —featured Simon Davidmann, CEO of Imperas; Bob Brennan, VP, GM at Intel Foundry Services; Himanshu Sanghavi, ASIC Engineering Manager at Meta; Rick O’Connor, President and CEO of the OpenHW Group; and Balaji Baktha, Founder and CEO at Ventana Micro. It was fascinating to listen to a variety of perspectives on the ways in which different companies are innovating with RISC-V.

One thing that stood out to me were the comments from Meta’s Sanghavi. He explained how his team is “developing RISC-V based ASICs for video transcoding, as well as machine learning applications.” Like a lot of companies, Meta evaluated multiple architectures before landing on RISC-V. He summed it up by saying that “as we stand today, we feel pretty good about our choice of RISC-V going back four years and the choice we made at that time.”

Redmond also made several memorable remarks during the discussion as she talked about how “RISC-V is truly inevitable” and “enables the best.” Simply put, Redmond shared that “there is no other architecture that allows you the design freedom and flexibility that RISC-V does.” For more details on this DAC panel, check out this recap blog post.

Leaving the conference, I was truly impressed by everything I learned about RISC-V’s influence across the industry. After listening to users and developers of RISC-V based products and services, one thing was abundantly clear: the future of design lies with RISC-V.

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