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Announcing The Fourth International Workshop on RISC-V for HPC

By February 19, 2024No Comments

The RISC-V HPC Special Interest Group is organising a workshop at ISC24, one of the leading High Performance Computing (HPC) conferences. The workshop will run on the 16th of May in Hamburg Germany, and the call for papers is now open!

The topic of this years ISC is Reinventing HPC, and RISC-V has the potential to do exactly that. The open nature of RISC-V can significantly benefit the HPC community by providing many more opportunities for specialisation. This increased choice, where the hardware can potentially be tuned and optimized for different the types of workloads, not only benefits performance but could also play an important role in energy efficiency as many computing centres look to decarbonise their activities.

In recent years the RISC-V HPC Special Interest Group have organised several workshops and BoFs at a range of HPC focussed conferences, including ISC, SC, and HPC Asia where we have been impressed with the general interest shown by the HPC community in RISC-V and keenness to learn more about the technology and explore the potential around RISC-V for future HPC workloads. Indeed, RISC-V Internationals own Mark Himelstein gave the keynote talk at the RISC-V for HPC workshop at SC23, which provided a fascinating view of what RISC-V is, where the standard is going and the potential benefits in adopting RISC-V.

In HPC, computational horsepower is used by scientists and engineers to tackle some of the grand challenges faced by society, ranging from increasing the accuracy of weather prediction to designing more fuel efficient aircraft engines. However, irrespective of the interest that RISC-V is gaining in the HPC community, currently supercomputers tend to rely on non RISC-V architecture CPUs which are often paired with GPU accelerators. One of the objectives of the HPC SIG is to drive adoption of RISC-V in HPC, and there are a whole range of recent developments in both the RISC-V hardware and software which have the potential to make this a reality and make RISC-V a more compelling proposition for HPC than ever before.

The purpose of the workshop at ISC is to bring together those already involved in RISC-V with the supercomputing community at-large. The success of these sessions at previous HPC conferences demonstrates a high level of commitment, so our objective is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators.

We hope to showcase a diverse set of RISC-V topics at the workshop, ranging from application porting and lessons learnt, to tools and hardware development. This workshop is a great opportunity to gain visibility and connections for researchers in the RISC-V HPC community. If you have been working on some topical and interesting RISC-V based HPC research, please submit a paper!  We are accepting both full papers on mature work and also work-in-progress papers on more embryonic activities. The deadline for submitting papers is 11th March 2024 (AoE) with more details on our website at

We hope to see you at the workshop in May!

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