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2021 RISC-V Week

March 30, 2021 @ 8:00 am - March 31, 2021 @ 5:00 pm CEST

“3rd RISC-V Meeting” on March 30-31

Online + Paris (Palaiseau) & Grenoble

The RISC-V architecture, which comes from academia, is challenging several communities.

  • It opens the architecture and hardware design communities to the dynamics of open source;
  • It eases the introduction of new technologies in the verification tool flow of IPs;
  • Language, compilation, operating system, security or safety communities can now influence the definition of hardware architectures;
  • More generally, it allows hardware, software and system communities to experiment together.

After the first 1st RISC-V Meeting in Grenoble in October 2018, and the 2nd RISC-V Meeting in Paris in October 2019, this 3rd RISC-V Meeting was originally scheduled to happen in real life in Rennes in November 2020. Due to the current pandemic it has been postponed and will finally take place on line and, if conditions allow, partly in real life with local sites in Rennes, Palaiseau (SW of Paris), and Grenoble. It will last two days: Tuesday March 30th and Wednesday March 31st, 2021.

This 3rd iteration will be open to students, academics and industrials.

The program will be made of multiple sessions, with a small number of short contributions followed by a time for group discussion. The program will also include a number of tutorials on key RISC-V issues and solutions, and high-level keynotes.


March 30, 2021 @ 8:00 am CEST
March 31, 2021 @ 5:00 pm CEST
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