Stay Connected With RISC-V
We send occasional news about RISC-V technical progress, news, and events.
RISC-V has emerged as a viable solution on academia and industry. Pushed by the success of RISC-V, many other open source hardware projects have started and it is certainly to be expected that even more of them will start in the near future. However, to use open source hardware for safety critical applications, we need a deep understanding of the way in which well established mechanisms for testing reliability could be integrated and deployed on the RISC- V ecosystem, and we need a clear knowledge on how such an ecosystem can be leveraged to improve security. To this end, this special session addresses issues related with the use of RISC-V based architecture in the context of security, reliability and testing. The topics covered by the session are timely and of interest of the attendees of ETS. RISC-V and open hardware in general are gaining momentum, and their diffusion in secure and safety critical applications expose them to classical challenges related with security and reliability typical of these application domains. Recent results demonstrated the suitability of the platform for these applications, but several challenges are still far from being completely solved. It is thus of crucial importance that designers are fully aware of current limitations and possibilities associated with the use of the RISC-V platform in safety critical applications, to addressed and exploit them in a correct and effective way.
|18:30 – 18:45||How RISC-V can help in security research|
|Frank K. Gürkaynak (ETH Zurich – Switzerland)|
|Abstract: In relatively short time RISC-V has had a remarkable impact on both academia and industry, presenting many exciting opportunities especially when used in connection with open source hardware. However, the problems we face in the security field are not automatically solved by having access to an open ISA and open source implementation of this ISA. In this talk, I will present how our group leverages RISC-V and open source hardware for security research, and explain what works well and where we see issues at the moment.|
|Speaker bio: Frank K. Gürkaynak has obtained his Ph.D. Degree from ETH Zürich, and is working as a senior scientist in the Digital Circuits and Systems Group of Prof. Benini as well as leading the Microelectronics Design Center of ETH Zürich.|
|18:45 – 19:00||Thwarting Differential Power Analysis Attacks on RISCV processors|
|Michael Hutter, Elke De Mulder, Helena Handschuh (Rambus – USA)|
|Abstract: In this talk, after a short introduction on side-channel attacks such as Differential Power Analysis (DPA) and on how challenging it is to protect RISCV processors against physical attacks in general, we will provide an overview of the state of the art solutions including those proposed by industry such as our Rambus Secure RISCV core as well as those proposed by academia such as IAIK, ETH and WPI’s approaches. We will then discuss in more details how different solutions offer different levels of protection, most notably gate-level masking in hardware, software only based solutions, instruction set extensions that allow for DPA-hardened coprocessors, protocol level solutions etc. We also discuss hardware-software co-design. Furthermore, we address the question of how to efficiently test such protections, and which testing strategies might offer the best results. Finally, we leave the audience with some open problems such as memory protection, fault attack protection and RISCV processor input-output interface protections.|
|Speaker bio: Michael Hutter is a Senior Principal Engineer at Rambus, Inc. His current responsibilities include the technical lead of secure hardware developments, DPA resistant solutions, and advanced products. He holds a PhD degree in computer science from Graz University of Technology, Austria. From 2011 until 2014, he worked as a post-doctoral researcher and lecturer at TU Graz where he received a venia docendi (Habilitation) in applied information processing and communications in 2016. He has authored and co-authored 60+ conference and journal publications and had served on technical program committees of international cryptography and security conferences such as CHES, DATE, COSADE, CARDIS etc.|
|19:00 – 19:15||SW-only and HW/SW support for diverse redundancy for high-integrity applications|
|Jaume Abella (Barcelona Supercomputing Center – Spain)|
|Abstract: Common Cause Failures (CCFs), where a single fault can lead to a system failure, are a challenge for safety-related systems (e.g. avionics, automotive, space) where high integrity is mandatory. Dual Core LockStep (DCLS), where two cores provide redundancy with sufficient independence (i.e. diversity), is the default solution. However, such a solution halves the number of user-visible cores in multicores. Our research investigates SW-only and HW/SW solutions to enable diverse redundancy without needing strict DCLS. We will present our recent work and ongoing research to enable both types of solutions on both general-purpose multicores as well as GPUs.|
|Speaker bio: Jaume Abella is a Senior Researcher at the Barcelona Supercomputing Center (BSC) since 2009, and CEO of Maspatechnologies S.L. He holds a PhD degree by the Universitat Politecnica de Catalunya (2005). Jaume leads BSC activities in multiple projects related to the hardware and low-level software design for high-performance safety-related real-time embedded systems, including H2020 De-RISC, H2020 SELENE, ECSEL FRACTAL, H2020 SAFURE, and ARTEMIS VeTeSS, with particular focus on functional safety, reliability, timing V&V, and dependability in general. Jaume worked at Intel Corporation from 2005 to 2009. Jaume holds 13 patents, and has published 200 papers in international peer-reviewed conferences and journals.|
|19:15 – 19:30||Towards Bridging the Gap between System-level and Structural Test for the RISC-V Platform|
|Nourhan Elhamawy, Jens Anders, Steffen Becker, Matthias Sauer, Stefan Wagner, Ilia Polian (University of Stuttgart and Advantest – Germany)|
|Abstract: Microprocessors implementing the open RISC-V instruction set and systems-on-chip on their basis are increasingly being considered for safety-critical applications. A prerequisite for their acceptance in domains such as automotive is the feasibility of test procedures established in such domains. System-level test (SLT) is widely employed by both semiconductor manufacturers and system integrators to guarantee the required quality levels, based on procedures, data formats and protocols that have grown over time and are supported by multiple parties. This talk will discuss the specific challenges in making SLT part of an open ecosystem enabled by the RISC-V instruction set, where some of the information required for SLT may not exist. State-of-the-art RISC-V implementations are compatible with standard design flows, which enables a straightforward use of conventional structural test procedures and design-for-testability approaches. However, SLT comes with intricate challenges ranging from an appropriate definition of fault detection to assessing fault coverage of test content defined on the application and operating system level. One challenge is to understand what are the unique detections by different SLT programs and how to best combine different programs such as maximize coverage while keeping test duration realistic. To this end, we will present first results on coverages achieved by structural and system-level test approaches on a popular RISC-V processor implementation and its submodules.|
|Speaker bio: Ilia Polian IP is a Chaired Professor of Hardware-Oriented Computer Science and the Director of the Institute for Computer Engineering and Computer Architecture at the University of Stuttgart, Germany. He co-authored over 200 publications About test methods, hardware-oriented security and emerging architectures and received two best paper awards. He is the Speaker of the DFG Priority Program Nano Security.|
We send occasional news about RISC-V technical progress, news, and events.