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edacentrum 3rd Workshop on RISC-V Activities

October 8, 2020

The workshop aims to stimulate the exchange of information among the attendees about already existing or planned RISC-V activities. The workshop provides a platform for how these activities can be extended across projects or to develop new ideas, activities and collaborations. This workshop has been initiated by the BMBF funded projects COMPACT, SAFE4I and Scale4Edge and will be executed in conjunction with the edaWorkshop20.

RISC-V Talks:
08:50 – 10:00
Session 1 (Invited Talks)
Moderator: Stefan Wallentowitz (Munich University of Applied Sciences, D)

09:00 Keynote:
Invited Talk: RISC-V Scale4Edge Ecosystem – Motivation and Objectives
Wolfgang Ecker (Infineon, D)

09:30 Keynote:
Invited Talk: RISC-V Software Ecosystem
Jeremy Bennett (Embecosm, UK)

10:15 – 11:15
Session 2 HW, Compiler and Verification
Moderator: Andreas Mauderer (Bosch, D)

10:15 A RISC-V based Edge Computing Platform with Interchangeable Cores Using 22FDX
Paul Palomero Bernardo (University of Tuebingen, D)
Adrian Frischknecht (University of Tuebingen, D)
Dustin Peterson (University of Tuebingen, D)

10:30 Energy Efficient RISC-V Implementations in 22 nm
Heiner Bauer (Technical University of Dresden, D)

10:45 A Compiler Comparison in the RISC-V Ecosystem
Mehrdad Poorhosseini (University of Oldenburg, D)
Kim Grüttner (University of Oldenburg, D)
Wolfgang Nebel (University of Oldenburg, D)

11:00 Efficient RISC-V Processor Verification via Cross-Level Testing
Vladimir Herdt (University of Bremen / DFKI, D)
Eyck Jentzsch (MINRES Technologies, D)
Daniel Große (Johannes Kepler University Linz, AT)
Rolf Drechsler (University of Bremen / DFKI, D)

11:15 – 11:45
Breakout Session 3
Moderator: Oliver Bringmann (U Tuebingen, D)

11:20 HW and RISC-V HW Ecosystem
Oliver Bringmann (U Tuebingen, D)

11:20 Verification
Vladimir Herdt (University of Bremen / DFKI, D)

11:20 Compiler + RISC-V SW Ecosystem
Kim Grüttner (OFFIS, D)

12:55 – 13:40
Session 4 Virtual Prototype (VP)
Moderator: Daniel Müller-Gritschneder (Technical University of Munich, D)

12:55 RISC-V Models for Verification, Software Development and Architectural Exploration
Larry Lapides (Imperas Software, US)

13:10 RISC-V core implementation in synthesizable SystemC-RTL
Juan Camilo Santana Miranda (Fraunhofer IIS, D)

13:25 A Configurable Virtual Prototyping Environment for Different RISC-V ISA Subsets
Peer Adelt (University of Paderborn, D)

13:40 – 15:05
Session 5 (Invited Talks)
Moderator: Andreas Vörg (edacentrum, D)

13:40 Keynote:
Invited Talk: CHIPS Alliance and Western Digital’s RISC-V Related Activities
Zvonimir Bandić (Western Digital, US)

14:10 Keynote:
Invited Talk: Collaboration and adoption Accelerate with RISC-V International with Live Q&A
Calista Redmond (RISC-V Foundation International, US)

14:50 RISC-V in Education
Stefan Wallentowitz (Munich University of Applied Sciences, D)

15:20 – 16:20
Session 6 Security
Moderator: Raik Brinkmann (OneSpin Solutions, D)

15:20 Security Issues in Hardware/Firmware interaction – Can a formal analysis of (just) the hardware help?
Johannes Müller (Technical University of Kaiserslautern, D)

15:35 Security and Trust Assurance of RISC-V Open-source Cores RocketCore and OpenHW CV32E
Sergio Marchese (OneSpin Solutions, GB)

15:50 Leveraging the RISC-V Ecosystem for Hardware Security: A Logic Locking Approach
Dominik Sisejkovic (RWTH Aachen University, D)
Rainer Leupers (RWTH Aachen University, D)

16:05 RISQ-V: Instruction Set Extensions and Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography
Tim Fritzmann (Technical University of Munich, D)
Debapriya Basu Roy (Technical University of Munich, D)
Johanna Sepúlveda (Airbus, D)
Georg Sigl (TU München, Fraunhofer AISEC, D)

16:20 – 17:00
Breakout Session 7
Moderator: Wolfgang Müller (University of Paderborn, D)

16:25 Virtual Prototype (VP)
Wolfgang Müller (University of Paderborn, D)

16:25 Security
Wolfgang Kunz (Technical University of Kaiserslautern, D)


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