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Co-located with ISC, Europe’s largest HPC conference, the goal of this workshop is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. There are numerous potential advantages that RISC-V can provide to HPC and, assuming the significant rate of growth of this technology to date continues, as we progress further into the decade it is highly likely that RISC-V will become more relevant and widespread for HPC workloads. Furthermore, recent advances in RISC-V make it a more realistic proposition for HPC workloads than ever before.
The open and standardised nature of RISC-V means that the large, and growing community, can be involved in shaping the standard and tooling. This is important from two perspectives, firstly the HPC community can help shape the future of RISC-V to ensure that it is suitable for the next generation of supercomputers. Secondly, whilst there are a wide variety of RISC-V CPUs currently available, the standard nature of the tooling means that very often the same software ecosystem comprising the compiler, operating system, and libraries will run across these whilst requiring few changes and there are opportunities for the HPC community to significantly contribute here.
This workshop aims to bring together those already looking to popularise RISC-V in the field of HPC with the supercomputing community at-large. By sharing benefits of the architecture, success stories, and techniques we hope to further popularise the technology and increase involvement by the community.
There is a call for paper detailing work-in-progress, position papers, or mature work on RISC-V for HPC, with the current submission deadline of 11th March 2024 (AoE). See the event website for updates regarding the deadline, full instructions around paper format and preparation, and the submission deadline. The event website will also be updated with the workshop schedule as this comes together in the coming months.
We send occasional news about RISC-V technical progress, news, and events.