Skip to main content
Loading Events

« All Events

  • This event has passed.

RVfpga Workshop at Zhejiang University, China

October 29, 2023

|Recurring Event (See all)
The same workshop on both days
Time:Oct 28th – Oct 29th 2023, 9AM – 5PM on each day
地点:Conference Room 211, Shaw Science Museum, Yuquan Campus, Zhejiang University (浙江大学玉泉校区邵逸夫科学馆 211 会议室)
*The workshop will be in Chinese;将会用中文授课

Register Now

Bring RISC-V to your course in computer architecture using RVfpga

This workshop shows how to use RISC-V to teach computer architecture and the design of systems on chip (SoCs). Let us empower you to teach next generation computer science, electrical and computer engineering students with hands-on real-world expertise in computer architecture and the RISC-V instruction set architecture.

What is the RVfpga workshop about?

RISC-V is a rapidly growing world-wide movement. It is open source and provides extensions, making it easier to target to various platforms. This RVfpga workshop presents a commercial RISC-V system targeted to an FPGA, discusses the theory, architecture, and course structure, and shows how to use the hands-on labs that are provided as part of the complete RISC-V FPGA (RVfpga) Course. The course explores the fundamentals of computer architecture using Western Digital’s open-source, commercial SweRV EH1 RISC-V core targeted to a Xilinx Artix 7 FPGA on Digilent’s Nexys A7 development board. Everyone will get hands-on experience with this FPGA platform and the software tools, enabling a fast start when you return to your university.

What will you learn?

The workshop shows how to quickly get the RISC-V FPGA system and RISC-V tools up and running. Then, we describe all of the RVfpga labs and show how to use and work through a selection of the labs hands-on. We also discuss how to integrate RVfpga into your curriculum.

Specific topics include:

* Installing tools (which can be done before the workshop)

* Targeting the SweRV EH1 RISC-V core to an FPGA

* Analyzing and modifying the RISC-V-core and memory hierarchy


Workshop Schedule: 9AM to 5PM


Draft Schedule:

– Welcome, Introductions and Set-up

– Introduction to the teaching materials and workshop


– Instruction and Hands-On Labs

Supporting Organisations:

– Overview of the Imagination University Programme, by Robert Owen (Imagination)

– The Digi-Key Academic Program, by YC Wang

>> Lunch Break and Networking

– Instruction and Hands-On Labs

– Feedback Forms


– How to fit RVfpga into your curriculum, Your next steps, Q&A

*The schedule for the day is subject to change. So that you can plan your travel, we will not start earlier than 9AM and our finish will be 5PM latest.



Liu Peng, professor and doctoral supervisor at Zhejiang University. Responsible for the completion of more than 10 national vertical projects such as the National 863 Project, the National Natural Science Foundation, basic preliminary research, and the Huo Yingdong Education Fund. Research areas mainly include computer architecture and microstructure, integrated circuit design, hardware security, and quantum computing. Research results have been published in top international journals and conferences such as IEEE Trans. Computers, ACM TACO, TVLSI, CHES, etc. He has published more than 170 academic papers and authorized more than 40 Chinese invention patents. Served as a member of the A-SSCC and VLSI-SOC technical committees. Served as a member of the Industry Maturity Working Group of the Information Technology Innovation Working Committee, and as one of the drafters formulated the chip group standard for the information technology application innovation information product maturity assessment system. Has mentored and trained more than 80 doctoral and master’s students. Won the second prize of Zhejiang University’s Quality Teaching Award. The course “Computer Composition and Design” he taught was awarded the 2022 Zhejiang University Huawei Intelligent Base Gold Course; he filmed the MOOC “Computer Composition and Design: RISC-V” and won the 2020 Zhejiang Province Online First-class course.
Xi Yuhao, a master’s student at the School of Information and Electronic Engineering, Zhejiang University. His research interests include computer system structure and processor design.
Liu Anlin, a master’s student at the School of Information and Electronic Engineering, Zhejiang University. His research interests include processor instruction systems and verification methods.

刘鹏,浙江大学教授, 博士生导师负责完成国家863项目、国家自然科学基金、基础预研、霍英东教育基金等10余项国家纵向项目。研究领域主要包括计算机体系结构及微结构、集成电路设计、硬件安全、量子计算。研究成果发表于IEEE Trans. Computers, ACM TACO, TVLSI,CHES等国际顶级期刊和顶级会议,已发表学术论文170余篇,授权中国发明专利40余件。担任A-SSCC、VLSI-SOC 技术委员会委员。担任信息技术创新工作委员会产业成熟度工作组委员,作为起草人之一制定了信息技术应用创新信息产品成熟度评估体系芯片团体标准。已指导培养博士硕士80余人。曾获浙江大学优质教学二等奖,主讲课程《计算机组成与设计》获2022浙大华为智能基座金课;拍摄MOOC《计算机组成与设计:RISC-V》,并荣获2020年度浙江省线上一流课程。


October 29, 2023
Event Categories:
Event Tags:


Imagination Technologies
View Organizer Website

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.