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UltraSoC Blog: RISC-V Workshop: Security, Scalability, And Super Mario

By May 16, 2018May 12th, 2021No Comments

UltraSoC participated in the 8th RISC-V workshop in Barcelona last week, which was a great success. It was fascinating to hear just how much, and how quickly, progress is being made by the RISC-V community. There were a few hundred attendees, ranging from big business, start-ups, through academia to hobbyists.
As sponsors of the event, and arriving in force with six staffers including our CEO, CTO, sales and engineering representatives, UltraSoC certainly made an impression. This reflects our commitment to and belief in the importance of the emerging RISC-V ecosystem.
A combination of our leading role in the RISC-V Debug Working Group, plus a barnstorming explanation of the benefits of UltraSoC’s technology by CTO Gajinder Panesar, ensured there was no shortage of interest around the technology demo at our booth. It wasn’t lost on the attendees that UltraSoC are the only company offering a RISC-V trace solution at this point in time, and our demos of run-control and instruction trace with SiFive and Andes cores attracted queues.
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