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Rambus Blog Post: Lowering Risks With RISC-V

By August 27, 2018May 12th, 2021No Comments

Reduced Instruction Set Computing Five (RISC-V) is an open Instruction Set Architecture (ISA) designed with small, fast, and low-power real-world implementations in mind. It describes the way in which software talks to an underlying processor, in a manner similar to the x86 ISA for Intel/AMD processors and the ARMv8 ISA for the latest ARM processors. However, unlike x86 ISA and ARMv8 ISA, the RISC-V ISA is open source.  Any party can build a processor that using RISC-V. Not only simply processing architecture, but with a substantial body of supporting software, RISC-V can be freely used by anyone, for any purpose, and useful in a wide range of devices.
In the wake of Meltdown, Spectre, and Foreshadow exploits found in modern CPUs, people are beginning to realize that modern CPUs may be designed for performance first, safety second. In Rambus’ CryptoManager Root of Trust, the RISC-V core is located on the same silicon as the general processor, but physically separated by a secure boundary. It can run algorithms and processes within that secure boundary to protect against a wide range of attacks, including side-channel attacks, and protect against software vulnerabilities and exploits. It can also prevent device cloning.
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