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MyNavi Article: RISC-V In Tokyo 2018 – SiFive's Cloud Design Service

By October 24, 2018May 12th, 2021No Comments

Held at Keio University of Hiyoshi, this year’s RISC-V Day Tokyo was a success. The event had about 250 attendees.
Professor Krste Asanović of the University of California, Berkeley contributed to the development of the RISC-V architecture for education purposes, but overtime the technology has become widely used and is considered practical and crucial in the semiconductor industry. The “V’ in RISC-V is the Roman numeral five, which stands for the fifth generation processor architecture developed at Berkeley.
To read more, please visit: note the article is in Japanese.

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