Embedded Computing Design Article: Imperas RiscvOVPsim Brings Free, Open-Source Modeling And Simulation To RISC-V Ecosystem

Imperas Software has released the RISC-V Open Virtual Platform Simulator (riscvOVPsim), a free simulator and open-source model of a single-core RISC-V CPU. riscvOVPsim acts as a reference instruction set simulator that delivers high-level simulation for development and compliance testing, allowing RISC-V software engineers to begin development before the availability of silicon and hardware engineers to accelerate design verification.
The open-source model in riscvOVPsim is a Fast Processor Model of current 32/64-bit RISC-V instruction set feature specifications that can be configured to any single-core RISC-V CPU variant. The model covers RISC-V User and Privilege specifications, and can be used as a platform target for developing bare metal applications.
 
To read more, please visit: http://www.embedded-computing.com/news/imperas-riscvovpsim-brings-free-open-source-modeling-and-simulation-to-risc-v-ecosystem.