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EE Journal Article: Microsemi Joins RISC-V Love Fest With SoC FPGA

By December 13, 2018May 12th, 2021No Comments

Processors and FPGAs go together like chocolate and peanut butter, but it took a few years to get the recipe just right. Early turn-of-the-millennium attempts included the Xilinx Virtex II Pro with an on-chip PowerPC processor core and Altera’s Excalibur device with an ARM922T processor core. These early products are considered market failures. Actually, Kevin Morris called the Altera Excalibur “a monumental flop” in his article titled “Shaking Up Embedded Processing.” Why? Because you can’t just plop an unconnected microprocessor core into the middle of an FPGA array and call it a finished product. There’s simply no added value there. Few designers want to waste time designing some sort of bog standard processing subsystem around a naked processor core, and no one wants to use precious, programmable LUTs to implement that processor subsystem once it’s designed.
The current trend of merging processor cores with hardened microprocessor subsystems together with FPGAs on one chip started early in 2010. Xilinx first revealed the Zynq “EPP” (Extensible Processing Platform) architecture during a short presentation at the Real Time & Embedded Computing Conference (RTECC) held in Santa Clara, California on January 26, 2010.
Earlier this month, at the first RISC-V Summit (aka “open-source processor love fest”), Microsemi announced a significant upgrade to the SmartFusion device concept by announcing its PolarFire SoC FPGA architecture. (No actual parts yet announced.)
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