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eeNews Analog Article: Mythic AI Adopts RISC-V Core From Codasip

By December 11, 2018May 12th, 2021No Comments
Machine-learning chip developer Mythic Inc. (Austin, Texas) has selected the configurable Bk5 RISC-V processor from Codasip Ltd. (Brno, Czech Republic) for use in future neural networking chips.
Mythic was founded in 2012 as Isocline Engineering Corp. and is adopting an analog “processing-in-memory” approach to neural network implementation
The Mythic Intelligence Processing Unit (IPU), which performs the inference step of deep neural networks inside the same flash memory array which stores the neural network’s weights and thereby delivers advantages in performance, cost, and power consumption compared with some more traditional systems that build inference processors in logic and move data to and from these processors.
The Codasip Bk5 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 5-stage in-order execution processor pipeline and offers optional caches, IEEE 1149.1 debug, branch prediction, and industry standard bus interfaces. Further, the Bk5 – like all Codasip RISC-V implementations – is configurable and extensible.

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