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Hackaday Article: VexRISC-V Exposed

By December 10, 2018May 12th, 2021No Comments

If you want to use FPGAs, you’ll almost always use an HDL like Verilog or VHDL. These are layers of abstraction just like using a C compiler for machine language or assembly code. There are other challengers such as SpinalHDL, which have small but enthusiastic followings. [Tom] has a post about how the VexRISC-V CPU leverages SpinalHDL make an extremely flexible system that is as efficient as plain Verilog. He says the example shows off why you should be using SpinaHDL.
Like a conventional programming language, it is easy to find niche languages that will attract a little attention and either take off  C++, Java or Rust, or just fade away. The problem is you can’t ever tell which ones are going to become major and which are just flashes in the pan. Is SpinalHDL the next big thing? We don’t know.
[Tom] had a RISC-V design, MR1, and in comparisons, the SpinalHDL implementation was better. He wanted to know why and the post is a result of his exploration.
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