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Sohu Article: Detailed RISC-V-Based AndeStar V5 Architecture Innovation And Application

By January 22, 2019May 12th, 2021No Comments

On Jan. 4 2019, the Zhishang Open Class officially launched the RISC-V series, focusing on the Chinese RISC-V ecosystem. In this RISC-V series, Hu Jin, senior field application manager from SiFive China, and Wu Jun, director of SoC platform, Wang Zhenwen, CEO of Core Technology, and Wang Shengwen, director of Andes Technology Marketing and Technology Services, will bring three sessions in succession.
The first two lectures are on Jan. 9 by Wu Jin, senior field application manager of SiFive China, and Wu Jun, director of SoC platform. The theme is “The ecological status and development examples of RISC-V”, and the core is on January 16th. The second lecture of Technology CEO Hu Zhenbo, entitled “Processor Design and Development for the Internet of Things”, attracted IC design engineers from well-known semiconductor companies such as Huawei HiSilicon, Ziguang Zhanrui, AMD, Intel, and Anba Semiconductor. The first two lectures in the Zhishi open class small program live broadcast reached over 6,000 listeners, including electronic engineers and teachers and students from Tsinghua University, National Defense Science and Technology University, Chinese Academy of Sciences, Harbin Institute of Technology and other related fields such as microelectronics, integrated circuits, computer science and technology.
To read more, please visit: Please note that the original article is in Chinese.

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