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SmartDV Supports RISC-V Movement With TileLink Verification IP For RISC-V Based Systems

By February 6, 2019May 12th, 2021No Comments

SmartDV Technologies, the proven and trusted choice for Verification IP, today introduced TileLink VIP to verify the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based system on chip (SoC) designs.
In making the announcement, SmartDV becomes the first VIP solutions provider to offer a smart way to verify the TileLink fabric and reduce verification time. According to Deepak Kumar Tala, chairman of SmartDV, “60-80 percent of a project’s resources are spent on verification to ensure design success. Given the enthusiasm for RISC-V and TileLink’s importance within the open source RISC-V ISA, investing in a VIP solution for TileLink was an easy decision.”
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