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RISC-V Foundation Finalizes Schedule For RISC-V Workshop Zurich

By April 11, 2019May 12th, 2021No Comments

The RISC-V Foundation has released the agenda for its RISC-V Workshop Zurich, to be held on the 11th-13th of June as part of the larger Week of Open Source Hardware (WOSH).
Following its call for speakers, which closed back in February, the RISC-V Foundation has firmed up the schedule for the three-day RISC-V Workshop Zurich 2019 – though only the first two of these days are open to the general public, with the latter being reserved for RISC-V Foundation members.
The agenda includes a keynote speech from Luca Benini, professor at host ETH Zurich, on RISC-V’s potential for energy-efficient computing spanning the spectrum from microwatt embedded systems to exascale supercomputers; official updates from RISC-V Foundation members Krste Asanovic and Ted Marena as well as representatives of the RISC-V Technical Committee; updates on projects including OpenPiton+Ariane, Efabless’ Raven, the PUMP-NN neural network library, the space-qualified Klessydra RISC-V microcontroller, and a talk on how to squeeze eight RISC-V cores into a $38 FPGA development board by Olof Kindgren; a look at the OpenSBI as well as a secure bootloader, protecting RISC-V processors from physical attacks, a look at an intrinsically secure RISC-V processor from Olivier Savry and Thomas Hiscock, and Helena Handschuh on an open source approach to system security; updates on open-source compiler toolchains, RISC-V development via QEMU, and development with FreeRTOS; a look at the debug and trace capabilities in the SweRV core from Western Digital; formal verification of the PULPino core; and a look at RISC-V commercial implementations from SiFive, CloudBEAR, and Syntacore.
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