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Imperas And Metrics Collaborate To Jump Start RISC-V Core Design Verification Using Open Source Instruction Stream Generator

By June 11, 2019May 12th, 2021No Comments

Imperas Software Ltd.the leader in virtual platforms and high-performance software simulation, today announced the collaboration with Metrics, working on the verification challenges required for RISC-V cores to achieve the required tape-out-ready quality for broad adoption by silicon designers. Imperas and Metrics will be demonstrating the early stages of this framework using the Google open source Instruction Stream Generator for RISC-V processors and Google cloud services at the RISC-V Workshop Zurich this week.
The Open ISA (Instruction Set Architecture) of RISC-V is enabling a new generation of devices based on an open flexible architecture that permits free adoption and implementation with custom instruction and extensions. In addition to the design freedoms, an open ISA also permits the development of ecosystems and IP supplier alternative options: which includes the traditional IP vendor business model, individual developments or collaborative open source projects.
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