Open Memory-Centric Architectures Enabled By RISC-V And OmniXtend

OmniXtend is a cache coherence protocol that encapsulates coherence traffic in Ethernet frames and can be used to scale memory-centric applications. Today’s data centers are struggling to keep up with the explosive bandwidth requirements of big data. In many applications, such as artificial intelligence, bioinformatics, and in-memory databases, we commonly run into practical limitations dictated by the maximum available size of main memory. Because this memory is controlled by the central processing unit (CPU), the system architecture is required to conform to the interfaces exposed by the CPU. This effectively fixes the ratio of memory-to-compute in any practical system, which is an impediment to scaling many memory-centric applications.
RISC-V is an open instruction set which has spawned numerous different processor microarchitectures. Many of these implementations are open-sourced, including the buses and messaging required for multiple CPUs to share cache and main memory. The cache coherency bus ensures that all caches in the system, whether they belong to CPUs, GPUs, FPGAs, inference accelerators, or other kinds of compute engines, see a synchronized picture of the main memory they share. This makes the software programmer’s task much easier.
 
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