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Imperas announce first reference model with UVM encapsulation for RISC-V verification

By February 28, 2020April 28th, 2021No Comments

Oxford, United Kingdom, February 24th, 2020 — Imperas Software Ltd.the leader in virtual platforms and high-performance software simulation, today announced the latest enhancements to its range of RISC-V reference models and solutions to support processor verification, with the leading commercial SystemVerilog hardware design verification environments provided by Cadence, Mentor, Synopsys, and also the Metrics cloud based tools. Working together with lead customers, industry groups and associations, and the Google Instruction Stream Generator (ISG) developers, Imperas has enhanced the OVPsim reference models to support the comparison with directed tests, the RISC-V Foundation’s compliance tests, and tests created by the open source Google random ISG. The new approach to encapsulate the reference models within a SystemVerilog UVM (Universal Verification Methodology) test bench to allows a side-by-side comparison (step and compare verification) of RTL and reference model within the same environment for an interactive transaction-based analysis.

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