Munich, Germany – April 23rd, 2020 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, announced today the official release of its new product, the Codasip SweRV CoreTM EH1 Support Package, which includes a free basic version. The package is designed to provide developers with comprehensive support for the Western Digital SweRV Core™ EH1, a production-grade RISC-V core developed by Western Digital Corp. (NASDAQ: WDC) last year and currently supported and available to the open-source community through CHIPS Alliance, an open-source development organization which seeks to provide a barrier-free environment to allow collaboration for open-source software and hardware code.
The SweRV Core EH1 is a 32-bit, 2-way superscalar, 9-stage pipeline core with performance of up to 4.9 CoreMark/MHz and a small footprint, with clock speeds of up to 0.8 GHz on a 28nm CMOS process technology. The first of Western Digital’s RISC-V-based SweRV Core family, it is intended for use in embedded devices that support high-performance applications.
The SweRV Support Package (SSP), developed by Codasip in cooperation with Western Digital, provides a comprehensive set of tools and components needed to design, implement, test, and write software for a SweRV Core-based system-on-chip, integrated into one smart ready-to-use working environment. Support for leading EDA flows, from open source to commercial, models and examples, documentation, are all included and backed by professional technical support.
The basic version of the SweRV Support Package is available free of charge at GitHub, offering integration of open-source tools and support via a dedicated discussion forum. The Pro version features integration of commercial EDA tools on top of the Free package contents, and includes personalized support via e-mail and phone, including expert advice and design reviews. Optionally, Codasip will also provide customization and a full verification service on request.
“The close ongoing cooperation with Western Digital and CHIPS Alliance has made it possible to deliver an exclusive commercial support suite for their production grade SweRV Core,” stated Dr. Karel Masařík, CEO of Codasip. “We are confident that the Codasip SweRV Support Package will enable open-source users to implement innovative SweRV-based chips across a variety of domains, benefitting everyone. Commercial companies will be able to deliver their projects on time and on budget while avoiding risks inevitably associated with innovation. Universities will enjoy the free version of the package and the cooperative nature of the solution. Overall, we hope to help the open hardware community make another big step in its progress.”
“Western Digital is committed to supporting the open RISC-V ecosystem and accelerating development of new open, purpose-built architectures,” said Dr. Zvonimir Bandić, senior director of Next Generation Platforms Architecture at Western Digital and Chairman of CHIPS Alliance. “We are pleased to offer this expanded support for the SweRV Core to the open-source community as part of our ongoing collaboration with Codasip. Together, the SweRV Core and the Codasip SweRV Core Support Package offer a compelling foundation for RISC-V innovation.”
The SweRV Core Support Package is available now directly from Codasip.
Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Munich, Germany, Codasip currently has offices in the US, China, and Europe, with representatives in Asia and Israel. For more information about our products and services, visit www.codasip.com.
Roddy Urquhart, Senior Director of Marketing