In an earlier post we pointed out that there may be hidden costs associated with deploying an open source RISC-V core. In the software world, Linux became a mainstream enterprise operating system when Red Hat provided a commercially supported distribution with professional support services. Western Digital and Codasip have had a similar vision to create a package that would enable companies designing chips to use the open source RISC-V SweRV Core family in an easy-to-use and low-risk manner.
There are some differences between deploying a RISC-V core in a chip and using Linux as an enterprise operating system. Let’s look at the challenges:
- For commercial chip design, the chances are that most design teams do not use open-source EDA tools; they use commercial tools for verification, synthesis and static analysis. These tools are from a variety of suppliers and the teams may even want to swap the tool used for a particular task from time to time. Also, designers may use a variety of Linux distributions on their computers. A challenge for using the open-source RTL is to be able to undertake design tasks effectively, regardless of the EDA tool chosen.
- Any core embedded in a system-on-chip (SoC) will require embedded software, and the software development needs to run in parallel with the SoC development. Again, teams need not only a suitable toolchain but also access to an instruction set simulator (ISS) and, in many cases, FPGA emulation.
- Ideally, hardware and software design teams should have a package capable of meeting the requirements of all aspects of using the core. Such a package needs to be robust, having had adequate testing, and be easy to deploy. It also needs to be maintained, as EDA and software development tools are updated regularly and the package needs to be able to work with current versions.
- Last but not least, IC designers and embedded SW developers need professional support through means such as support tickets, phone calls and even on-site visits to be sure that help is available when needed, otherwise the risk of exceeding budget and not meeting the deadline is high.
In case of Western Digital’s open SweRV Core, all these challenges are going to be solved by the SweRV Support Package (SSP) which was pre-announced in December 2019. Since then, Codasip and Western Digital have been working on it diligently, developing components and combining them with existing open-source tools for a unique result. The package is going to provide a comfortable, ready-to-use integrated environment and all the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. This will include not only the currently available SweRV Core EH1 but also the next SweRV Cores EH2 and EL1. Watch this cool short video by Western Digital’s Zvonimir Bandić to get a taste of the SweRV cores and the Support Package!