Webinar: Multicore RISC-V Designs in AI & Machine Learning Applications | Imperas

 
Two meetings hosted on Wednesday May 6 to learn about Multicore RISC-V Designs in AI & Machine Learning Applications

Imperas, Andes, and UltraSoC invite SoC designers developing next generation devices to learn how to better optimize,  test, and evaluate multicore RISC-V designs for AI inferencing and machine learning applications.This webinar covers the latest challenges being faced by designers when migrating AI/ML applications to custom SoCs with RISC-V to accelerate complex algorithms and applications. While highlighting new application examples, many of the techniques and insights can equally be applied to any RISC-V based SoC design.This webinar will cover the key SoC design stages of:

•  Architectural exploration – Software driven prototype analysis with virtual platforms
• RISC-V core configuration – Optimized features for cores and processor sub-systems
• Full on-chip instrumentation – Debug and trace, and on-chip performance monitors

The webinar will be hosted by Mike Ingster, President and Founder of Quantum Leap Solutions (QLS), and will conclude with a Q&A session with the presenters.
“Moving an SoC solution from proof-of-concept to prototype stage and into volume production requires close alignment of multiple tools, techniques and methodologies to achieve first pass silicon success. RISC-V offers designers greater freedom and opportunities. And by leveraging the expertise of partners Imperas, Andes and UltraSoC, RISC-V designs can deliver a faster time to market.”