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RISC-V: How an Open ISA Benefits Hardware Security | Drew Fustini | Webinar (YouTube)

By September 23, 2020September 1st, 2021No Comments

About Webinar:
Ten years after the project was launched inside UC Berkeley, RISC-V is an open instruction set (ISA) that is enabling a growing number of open-source processor implementations. ETH Zurich implemented a RISC-V microcontroller core which has been adopted by non-profit lowRISC for the OpenTitan project in collaboration with Google. This project aims to provide a reference design to build a more transparent and trustworthy Root of Trust chips. I will be exploring this and other security projects that are benefited from open source design at the chip level.

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