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RISC-V’s CPU Verification Challenge | EEWeb

By September 3, 2020November 13th, 2020No Comments

RISC-V is gaining attention throughout the semiconductor industry. It offers the lure of an open-source solution that anyone can leverage to create their own CPU or custom accelerator.

Of course, dig deeper and challenges emerge. RISC-V is new and does not have the benefit yet of years of field-proven experience. This means that a carefully chosen and executed CPU verification strategy is essential. It also means that the availability of a “golden reference model” is a critical component that must be secured. Without a known good reference, it is impossible to have confidence in verification results. Having a custom instruction set simulator (ISS) is vital to success.

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