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PLS Expands Architecture Support: UDE Now Also Supports Debugging of RISC-V-based Devices and Cyclone V FPGAs | Staff, EE Journal

By October 6, 2020November 2nd, 2020No Comments

Lauta (Germany) / Cupertino (CA), October 06, 2020 – The Universal Debug Engine® (UDE), the modular debug, test and system analysis tool from PLS Programmierbare Logik & Systeme, now also supports the open and license-free RISC-V architecture and Intel Cyclone V SoC FPGAs.

Read the full press release.

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