Skip to main content
In the News

Renesas signs deal with open source ARM competitor | By Nick Flaherty

By October 1, 2020November 3rd, 2020No Comments

Renesas Electronics has signed a technology IP cooperation deal with Andes Technology for RISC-V based embedded CPU cores and the associated SoC development environment.

Renesas selected the AndesCore 32-bit CPU cores, based on the open source RISC-V instructin set architecture, to embed into new application-specific standard products that will begin customer sampling in the second half of 2021.

Read the full article.

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.