The VIU7-256 is SiFive’s first vector CPU. At the recent Linley Fall Processor Conference, the company introduced the new 64-bit core, built on the newest RISC-V standard. Although the design processes 512-bit vectors, the vector unit is only 256 bits wide (hence the -256 designation), so it requires two cycles per vector computation. By interleaving vector-load and vector-compute instructions, however, the design can achieve full utilization using only one instruction slot per cycle. Preliminary RTL is shipping now.