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Talk of configuring a base processor or adding custom extensions to resolve hardware-software design tradeoffs in a system on chip (SoC) is not new. This has been a key part of the value proposition espoused by the RISC-V community, with much information publishe don its benefits, like this one, “A guide to accelerating applications with just-right RISC-V custom instructions.”

In designing a system for many products today, power consumption, performance and die area constrain a lot of the complex artificial (AI) and machine learning (ML) SoC requirements.

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