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SAN FRANCISCO, Dec. 8, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that the organization will highlight OmniXtend advances in a presentation at the RISC-V Summit, taking place virtually from Dec. 8-10, 2020. The CHIPS Alliance plans to work with RISC-V International to standardize an open unified memory coherency bus leveraging OmniXtend to foster innovation for data-centric applications.

“As RISC-V is increasingly being considered for high end data center and enterprise applications, there is a need for seamless cache-coherent sharing memory systems,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance, and senior director of next-generation platforms architecture at Western Digital. “CHIPS Alliance is cooperating with RISC-V to standardize on a unified memory fabric and leverage OmniXtend, which allows heterogenous systems that use TileLink cache-coherence protocol to share the memory coherently. We see a unique opportunity because RISC-V is freely open, while other architectures don’t open up the coherency bus, with RISC-V we can create an open unified memory standard to accelerate innovation for data-centric, heterogeneous applications.”

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