The RISC-V instruction set architecture (ISA) leverages the power of open standard collaboration to enable freedom of innovation in computing design. This architecture has been implemented in a new synthesizable VHDL model of a processor called NOEL5. Released by Cobham Gaisler, NOEL5 complements the line of widely used radiation-tolerant LEON processors, enabling, amongst others, space missions. In its quest to create the first fully European hardware and software platform based on RISC-V ISA, the EU-funded project De-RISC has achieved its first milestones for space and aerospace designs. “The project is using Gaisler’s NOEL-V (LEON backwards) existing 64bit RISC-V processor in VHDL that shares many elements with the latest LEON5 core as the basis for the multicore design,” eeNews Europe reports. Summing up in part with regard to hardware, a De-RISC post on its first anniversary says “the project has developed the first version of the De-RISC MPSoC platform and the Performance Monitoring Unit, integrating observability (Cycle Contention Stack, Request Duration Counter) and controllability capabilities (Maximum-Contention Control Unit).” Cobham Gaisler is one of the four-member project consortium including also Barcelona Supercomputing Center and THALES, with Fent Innovative Software Solutions as coordinator.