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Throughout 2020 we have been hard at work developing proper, portable SystemVerilog support for multiple open-source FPGA and ASIC design tools used by us and our customers, most notably Yosys and Verilator. We strongly believe that the support is a necessary step in building a collaborative ecosystem and scalable and reproducible CIs, especially publicly accessible ones that are common in multi-organization projects such as OpenTitan and CHIPS Alliance. Leading the efforts towards achieving this goal, we’ve been developing a fully open source SystemVerilog parsing flow for Yosys and Verilator using UHDM and Surelog, achieving an important milestone: being able to fully parse, synthesize and simulate OpenTitan’s Ibex core directly from the SystemVerilog source.

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