Oxford, UK – December 8th, 2020 – Imperas Software Ltd., the leader in RISC-V processor verification technology, today confirmed the selection by Silicon Labs (NASDAQ: SLAB) of the Imperas RISC-V reference model as part of their RISC-V processor verification work. RISC-V processor verification can be the most complex of tasks within an SoC verification plan and to address the flexibility and configurability of RISC-V it is important that the reference model supports user and privilege modes plus all the standard ratified RISC-V specification variant options. In addition, to support the chip design schedules the refence model also needs to maintain configurability options for all the specification subset references as a dependable golden reference model for verification over the full lifetime of the project design phase and support future software development.