Skip to main content
In the News

The design of scalar AES Instruction Set Extensions for RISC-V |

By December 3, 2020December 4th, 2020No Comments
  • Ben MarshallDepartment of Computer Science, University of Bristol
  • G. Richard NewellMicrochip Technology Inc., USA
  • Dan PageDepartment of Computer Science, University of Bristol
  • Markku-Juhani O. SaarinenPQShield, UK
  • Claire WolfSymbiotic EDA
Keywords: ISE, AES, RISC-V


Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE. We survey the state-of-the-art industrial and academic ISEs for AES, implement and evaluate five different ISEs, one of which is novel. We recommend separate ISEs for 32 and 64-bit base architectures, with measured performance improvements for an AES-128 block encryption of 4x and 10x with a hardware cost of 1.1K and 8.2K gates respectively, when compared to a software-only implementation based on use of T-tables. We also explore how the proposed standard bit-manipulation extension to RISC-V can be harnessed for efficient implementation of AES-GCM. Our work supports the ongoing RISC-V cryptography extension standardisation process.

Go to the web page.

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.