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This article is derived from a talk at the RISC-V Summit in December 2020 that Bill McSpadden, principal verification engineer at Seagate Technology, gave on the challenges and experiences his team faced in the verification of two custom RISC-V processor cores. While a technical presentation at a technical conference may not be completely unexpected, the unique part was the frank acknowledgment that without any hype or fanfare the team tackled some of the most challenging verification problems in the industry today—how an experienced SoC team can verify a custom RISC-V processor. This article captures some of the highlights of the presentation and includes extra information from the tool suppliers Valtrix and Imperas.

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