Verifying a RISC-V Core-Based Design: A Primer

This article focuses on providing a jump start on RISC-V development. It shows how to build a verification environment quickly involving a RISC-V core and required peripherals based on selected applications.

RISC-V is an open-source instruction set architecture (ISA) specification. It is a general-purpose ISA developed at U.C. Berkeley, which is designed for supporting a wide variety of applications, from micro-power embedded devices to high-performance cloud server multi-processors, and is freely available for anyone to build a processor core compliant to its ISA. Because it is open-source, it is possible to customize the processor’s core and still be compliant to the RISC-V ISA, which has led to a rapidly-growing ecosystem in the market based on application requirements. All these custom-based processor ecosystems are used for various applications by integrating required peripherals. Many companies/organizations have developed RISC-V cores for targeted applications and made them available for further enhancement via open source.

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