Verification In The Open Source Era | Brian Bailey, Semiconductor Engineering

By RISC-V Community NewsMarch 26, 2021March 29th, 2021No Comments

What does open-source verification mean in the context of a RISC-V processor core? Does it provide free tools, free testbenches, or the freedom to innovate?

Read the article.

Previous PostIn $20bn push, Intel hopes to make US chip-making great again | Aljazeera
Next PostInstructor-led course now includes hands-on labs with a RISC-V based emulated development target | Behan Webster

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.

Verification In The Open Source Era | Brian Bailey, Semiconductor Engineering

Previous PostIn $20bn push, Intel hopes to make US chip-making great again | Aljazeera

Next PostInstructor-led course now includes hands-on labs with a RISC-V based emulated development target | Behan Webster

Stay Connected With RISC-V