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RISC-V boffins lay out a plan for bringing the architecture to high-performance computing | Gareth Halfacree, The Register

‘The group is united in making RISC-V an option in HPC,’ says SIG-HPC chair

RISC-V International, the nonprofit at the helm of the free and open-source CPU instruction set architecture, says it is writing a high-performance computing (HPC) roadmap of “new features and capabilities.”

For an architecture which only began life at the University of California, Berkeley, in 2010, RISC-V has enjoyed considerable success.

A wealth of products based on RISC-V are already in the market, with more arriving regularly, but the majority of these, like Seagate’s storage processor designs and the OpenTitan root-of-trust (RoT), target embedded or otherwise less performance-critical applications.

RISC-V International, though, believes there are more strings to its bow. In an announcement from member Dr John D Davis, chair of the RISC-V Special Interest Group on High Performance Computing (SIG-HPC), it has set out its stall for taking over the performance end of the market.

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