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Segger and Codasip Announce Cooperation on RISC-V

By RISC-V Community NewsJune 22, 2021June 25th, 2021No Comments

Monheim am Rhein & Munich, Germany – June 22nd, 2021 – SEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully support Codasip’s RISC-V processors, right out-of-the-box.

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Segger and Codasip Announce Cooperation on RISC-V

Previous PostCodasip Announces A71X RISC-V Application Core with Dual-Issue Capability

Next PostSiFive aims to challenge Arm with new tech, pairs with Intel on effort | Stephen Nellis, Reuters

Stay Connected With RISC-V