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Week In Review: Design, Low Power | Jesse Allen, Semiconductor Engineering

By July 2, 2021July 12th, 2021No Comments

Imperas and Valtrix inked a multi-year distribution and support agreement that makes Imperas simulation technology and RISC-V reference models available pre-integrated within Valtrix STING for RISC-V processor verification. The combined solution covers the full RISC-V specification for user, privilege, and debug modes, including all ratified standard extensions, and the near ratified (stable) specifications for Bit Manipulation, Crypto (Scala), DSP, Hypervisor, and Vectors. STING plus Imperas is also upgradable to add support for custom instructions and extensions.

Read more updates here.

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