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Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Picocom has deployed the Cadence® Palladium® Enterprise Emulation Platform to accelerate the verification and pre-silicon software validation of its system-on-chip (SoC) designs for 5G open radio access network (RAN) applications. Using the Palladium emulation platform, Picocom achieved faster hardware and software integration, experiencing an emulation speedup of 1000X when compared with RTL simulation.

The Palladium emulation platform gave Picocom the ability to bring up system software on RISC-V cores in advance of silicon being available. Using the Palladium emulation platform, Picocom took advantage of fast, predictable compile and was able to quickly debug its design. Picocom also met its power budget requirements using the Palladium Dynamic Power Analysis (DPA) feature, the Cadence Joules™ RTL Power Solution and the Cadence Voltus™ IC Power Integrity Solution to identify, capture and analyze power activity. To run efficient interface testing, Picocom utilized the Cadence SpeedBridge® adapters for PCI Express® (PCIe®) 4.0, USB 3.0 and Ethernet. Additionally, Picocom’s international team of engineers took advantage of the Palladium emulation platform’s remote accessibility, which allowed them to seamlessly work together to validate their designs.

Read the full announcement.

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