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New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The Register

By September 15, 2021No Comments

The SweRVolf project, a fully open system-on-chip designed as a reference platform for Western Digital’s RISC-V SweRV cores, has announced a major new release promising lower barriers to entry for those looking to experiment.

“Western Digital released the first of the SweRV cores, EH1, in 2018,” Olof Kindgren, senior digital design engineer at Qamcom and director at the Free and Open Source Silicon (FOSSi) Foundation, told The Register.

“While it was an amazing core, and the fastest 32-bit RISC-V core at least at that time, they were new to the world of open-source silicon and asked me what they should do to make it easier for others to pick it up.

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