An Instruction Set Architecture (ISA) is like the DNA of a computer. It’s what makes Arm®-based processors Arm, x86-based CPUs Intel®, and so on. RISC-V is a free and open ISA that was first introduced in 2010. Under the stewardship of RISC-V International, RISC-V has seen an explosive growth in interest from silicon vendors, software developers & academics, creating a truly global community.

Zephyr first introduced support for the RISC-V architecture in early 2017. Next came a growing list of RISC-V boards, which includes both processors and “soft-cores” used by FPGAs. In fact, it seems like every new RISC-V device that comes to market targets Zephyr first. This is due in part to the technical capabilities of Zephyr as well as the shared community of users who value open collaboration and Open Source.

This year for Open Source Summit + Embedded Linux Conference (OSS+ELC), organizers from RISC-V & the Zephyr Project decided to join forces on a combined co-located event in-person in Seattle. It’ll be a packed morning of talks, Birds of a Feather (BoF) round table discussions and demos. As an early preview, I’ll be giving a lightning talk showing off how we integrate Zephyr, our IoT platform & the latest RISC-V MCU from Espressif Systems, the ESP32-C3.

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