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The RVSoC Project is a research and development project of the RISC-V computer system targeting FPGAs in Verilog HDL at Arch Lab, Tokyo Tech.

RVSoC (RISC-V System on Chip) is a portable and Linux capable RISC-V computer system on an FPGA.

This system can be implemented on an FPGA with fewer hardware resources, and can be implemented on low cost FPGAs or customized by introducing an accelerator.

The source code of this system is written in Verilog HDL.

RVSoC includes

  • RVCoreM: 12-steps multi cycle processor (Not Pipelined)
  • RVuc: 4-steps multi cycle processor for I/O (Not Pipelined)
  • MMU: Sv32 address translation unit and TLB
  • Others

Find out more about the RVSoC Project.

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